Low-power, high speed and performance of double-tail dynamic comparator with conditional activation in 45 NM CMOS technology
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Author |
K. Madhava Rao, T. Vasudeva Reddy, Jyothirmai Joshi, V. Srilatha Reddy, T. L. Kayathri and Kellampalli Ramesh Babu
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e-ISSN |
1819-6608 |
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On Pages
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330-340
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Volume No. |
21
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Issue No. |
6
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Issue Date |
May 20, 2026
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DOI |
https://doi.org/10.59018/032642
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Keywords |
power consumption, energy efficiency, double-tail dynamic comparator, and performance enhancement.
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Abstract
High-performance and energy-efficient electronic devices are needed in the applications of the Analog-to-Digital Converters (ADCs) that operate at high speed and with low power consumption. Since ADCs provide good processing in digital circuits by converting analog signals to digital signals, i.e., digital data, they are fundamental to modern electronics. The comparator, or the key component of an ADC, discriminates against voltage levels and is an important part of defining the conversion speed and precision. This research aims at achieving a low power, high speed double-tail dynamic comparator that is desired in Successive Approximation Register (SAR) ADCs. (SAR)ADCs find extensive application in sensor interface, wireless communications, and biomedical equipment applications, where their performance and power efficiency are of great concern. The comparator provides precise decision making, consuming a minimum amount of power, which also directly impacts the efficiency of SAR ADCs. The proposed design consumes 32.61 uW of power, which makes the implementation suitable for low-power VLSI applications with a proprietary compiler and 45nm technology that ensures the best design to optimize efficiency and performance.
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